Memory devices find ubiquitous use in computing devices. Dynamic random access memory (DRAM) is commonly used as working memory in computing devices. The working memory is often volatile (it loses state if power is interrupted to the system), and provides temporary storage for data and programs (code) to be accessed and executed by the system processor(s).
There are multiple types and variations of DRAM (one example being synchronous DRAM (SDRAM)). Being dynamic, DRAM requires continuous or regular refreshing of the data bits stored in the memory device. The refreshing is generally controlled by a memory controller, which periodically accesses the data bits in the memory device.
Each memory cell in a DRAM is typically constructed from a single transistor and a single capacitor and is called dynamic because its data decays and becomes invalid due to various leakage current paths to surrounding cells and to the substrate. Therefore, to keep the data in the cells valid, each memory cell is periodically refreshed. Data in the DRAM cell array is refreshed every time it is read out of the cell array into the sense amplifiers and subsequently rewritten into the cell. Memory that is not read is refreshed by a specific refresh operation.
The memory controller is responsible for periodically performing refresh maintenance operations on the memory cell array. Every row of the memory array needs to be refreshed before the data in the row decays to an invalid state. During self-refresh mode the DRAM device is responsible for performing the refreshes.
The refresh cycle time (tRFC) of DRAM continues to grow with DRAM densities and it starts impacting isochronous bandwidth and worst case latency numbers. Isochronous bandwidth refers to bandwidth guarantees on the memory subsystem.